FreeCourseWeb.com    Tutorials    IT & Software    Xilinx VIVADO Beginner Course for FPGA Development in VHDL

Xilinx VIVADO Beginner Course for FPGA Development in VHDL

 freecourseweb0,

Learn how to Create VHDL Design,Simulation Testbench & Implementation with Xilinx VIVADO & FPGA: from Basic to Advanced.

“Learn VIVADO Development from Basic to Intermediate Level!!!”

What you’ll learn

  • Idea of VHDL Programming , VIVADO Design Methodology and Designing/Implementing Design in Zynq FPGA-ZedBoard.
  • Use fundamental VHDL constructs to create simple designs. Understanding the Conditional Statements in VHDL..
  • Design Simulation testbench on VHDL and simulating the designs..
  • Design with structural design methodology on VHDL..
  • Designing Decoder, Adder, Register and Counter in VHDL and Implementing in ZedBoard.
  • Implementing State Machine in VHDL; Designing/Implementing Sequence Detector.

Course Content

  • Section 1_Introduction and Overview of VHDL, VIVADO & Zynq –> 5 lectures • 1hr 1min.
  • Simulating VHDL code with Testbench –> 1 lecture • 19min.
  • Conditional Statements in VHDL –> 3 lectures • 31min.
  • Section 4_A Combinational Circuit Design(Half Adder Design) with VHDL in VIVADO –> 3 lectures • 35min.
  • Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL –> 1 lecture • 8min.
  • Section 5 Structural Design with VHDL (Full Adder Design using Half Adder) –> 2 lectures • 26min.
  • Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL –> 3 lectures • 38min.
  • Section 7 Finite State Machine Design:Sequence Detector Design/Implement in VHDL –> 1 lecture • 19min.
  • ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm) –> 3 lectures • 49min.
  • VHDL Reference Guide (From Basic Design to FSM Examples) from Digitronix Nepal –> 1 lecture • 15min.
  • Bonus Lecture –> 2 lectures • 1min.

Xilinx VIVADO Beginner Course for FPGA Development in VHDL

Requirements

“Learn VIVADO Development from Basic to Intermediate Level!!!”

This Course is of VHDL Programming from Basic (logic gate design) to Advance Design (Structural Design and State Machine Design). After completing the course student will get idea of VHDL programming design methodology, VIVADO Design Flow, Zynq Architecture, Creating Simulation Testbench, Conditional Statements, Combinational Circuit Design with VHDl, Sequential Circuit Design, Structural Design in VHDL and State Machine Design in VHDL.

In each section we have included Lab session on VIVADO which have been implemented on Zynq Board (i.e ZedBoard) FPGA, so Student will get complete design skill on VHDL with VIVADO.

You guys can Learn the course while using ISE Design Suit.While VIVADO is successor of ISE so this Course and VHDL Design Methodology is same for ISE based design so do not scare about VIVADO because of it just a latest version of Design tool than ISE.

The Top Level Outlines of the Course is:

  1. Basic Digital Design with VHDL and VIVADO Tool
  2. Creating Testbench on VHDL and Simulating with VIVADO Tool
  3. Combinational  Circuit Design in VHDL: Decoder Design,
  4. Sequential Circuit Design in VHDL: BCD Counter Design and implementation on ZedBoard
  5. Implementing digital design lab on Xilinx Zynq Boards: ZedBoard and Zybo
  6. Structural Design in VHDL: Creating Full Adder using Half Adder
  7. State Machine Design : Designing Sequence Detector in VHDL
  8. 8-bit ALU Design and Simulation in VHDL
Get Tutorial