From Netlist to GDSII: Learn Floorplanning, Placement, CTS, Routing, and Timing Closure using Industry-Standard EDA Tool
Physical Design, commonly known as Place and Route (PnR), is a cornerstone of the VLSI (Very Large Scale Integration) industry. It is the stage where the logical representation of a circuit (the netlist) is transformed into a physical layout that is manufacturable. Mastering this flow is essential for anyone aiming to work as a Physical Design Engineer, CAD Engineer, or ASIC Flow Engineer.
What you’ll learn
- Complete PnR Flow: Understand the step-by-step process of Physical Design from Netlist to GDSII..
- Tool Proficiency: Gain hands-on experience with industry-standard Cadence PnR tools..
- Floorplanning: Master techniques for die area estimation, I/O placement, and macro placement to optimize chip layout..
- Power Planning: Design robust power grids (power stripes/rings) to mitigate IR drop and electromigration..
- Placement Optimization: Perform standard cell placement and resolve placement-related congestion and timing issues..
- Timing Analysis: Analyze static timing reports and apply optimization techniques to fix setup and hold violations..
- Clock Tree Synthesis (CTS): Build balanced clock trees with low latency and skew..
- Routing: Execute global and detailed routing to connect all nets without design rule check (DRC) violations..
- Chip Finishing: Execute final steps including metal fill insertion and generating the final GDSII stream file for tape-out..
Course Content
- Physical Design: PnR with Cadence –> 10 lectures • 3hr 58min.
Requirements
Physical Design, commonly known as Place and Route (PnR), is a cornerstone of the VLSI (Very Large Scale Integration) industry. It is the stage where the logical representation of a circuit (the netlist) is transformed into a physical layout that is manufacturable. Mastering this flow is essential for anyone aiming to work as a Physical Design Engineer, CAD Engineer, or ASIC Flow Engineer.
This course offers a comprehensive, hands-on journey through the entire PnR flow, from initial data setup to final GDSII generation. We will utilize industry-standard Cadence tools to bridge the gap between theoretical VLSI concepts and real-world implementation. Unlike courses that focus solely on theory, this curriculum is structured to simulate the actual workflow of a physical design engineer. We will begin by understanding the critical input files—the netlist, LEF/DEF, and timing constraints (SDC)—that define the design.
From there, we will dive deep into the core stages of the flow. You will learn how to perform Design Import, followed by strategic Floorplanning where we define die area, core boundaries, and I/O placement. We will cover robust Power Planning to ensure reliable power distribution across the chip, preventing electromigration and IR drop issues. The course then moves into the algorithmic world of Placement, where we analyze congestion and timing. A significant portion is dedicated to Timing Analysis and Optimization, teaching you how to fix setup and hold violations before moving on to Clock Tree Synthesis (CTS) . Finally, we will navigate the complexities of Routing, handle Chip Finishing steps such as metal fill insertion, and conclude with a Practical Lab where you will run the full flow and export the final GDSII database. By the end of this course, you will have a portfolio-ready project and a deep understanding of how a chip is physically built.