Learn System Verilog for Design and Verification with lots of hands on exercises
Learn all the concepts of System Verilog in depth with lots of hands on programs and quizzes. Also create a project in System Verilog utilizing different verification constructs and concepts.
What you’ll learn
- Understand and Apply SystemVerilog Syntax and Constructs- Learners will be able to write syntactically correct SystemVerilog code with all its constrcuts..
- Design and Simulate Digital Circuits Using SystemVerilog and industry-standard simulation tools (e.g., ModelSim, QuestaSim)..
- Implement Testbenches Using Object-Oriented Programming (OOP) Features.
- Build and Use Constrained Random Testbenches and Functional Coverage Models.
- Lots of Hands On Coding Exercise will give confidence to students..
Course Content
- Introduction –> 1 lecture • 6min.
- System Verilog Arrays –> 1 lecture • 49min.
- System Verilog Classes (OOPS Concept) –> 2 lectures • 54min.
- System Verilog Event Regions –> 1 lecture • 12min.
- System Verilog Interface –> 1 lecture • 16min.
- System Verilog Clocking Block –> 1 lecture • 18min.
- System Verilog Assertions –> 1 lecture • 18min.
- System Verilog Interprocess Communication –> 1 lecture • 17min.
- System Verilog Program Block –> 1 lecture • 9min.
Requirements
Learn all the concepts of System Verilog in depth with lots of hands on programs and quizzes. Also create a project in System Verilog utilizing different verification constructs and concepts.
- Why System Verilog – What is the need for system verilog and what were all the challenges before System verilog standard and how system verilog solved them
- Data Types and constructs – Different data type and constructs which were added in the system verilog which eases out development and development of complex verification environments faster
- Threads / Inter-process communication/synchronization – New constructs like Semaphore, Mailbox, Events which got added for inter process communication and how to use them efficiently
- Classes and Randomization – Object oriented programming concepts to write extendable and maintainable testbenches along with randomization support for faster verification closure.
- Interfaces – Support for faster RTL/testbench development using interfaces/modports – Write less code and do more
- Coverage – How to make sure we are done with verification of Chip – Write & measure coverage.
- Assertions – Write checks closure to design
- Program Block – Avoid races using Program blocks
- Clocking Block – Avoid races in design and testbench using clocking blocks
- DPI (Direct Programming Interface) – Interface System verilog with C and other languages using System verilog DPI
- Project
- Design a synchronous FIFO with System verilog and create verification environment using advance features of system verilog like Queues, Classes, Randomization interface, coverage etc.