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Learn FPGA design with VHDL : Sobel Filter Edge Detection

Understand and build an edge detector based on Sobel filter from scratch in VHDL

As part of the “Learn FPGA Design with VHDL” hands-on series, this module focuses on implementing the Sobel edge-detection filter — a foundational building block for feature extraction, and image processing on FPGAs.

What you’ll learn

Course Content

Requirements

As part of the “Learn FPGA Design with VHDL” hands-on series, this module focuses on implementing the Sobel edge-detection filter — a foundational building block for feature extraction, and image processing on FPGAs.

In this course, you will:

This engineering project is fun and will give you lot of skills in different subjects.

By the end, you’ll be able to implement a Sobel edge detector in VHDL. Through this process, you will gain knowledge in image processing. You will also get accustomed to finite state machines, arithmetic on signed and unsigned numbers, RAMs and ROMs, multiplexing and hardware design in general. You will also learn to automate your project. Running all your project with one command is fun, you will gain the sight of applying it to your own projects.